←回DISP實驗室成員介紹

魏維毅 Wei-Yi Wei



《Autobiography》

    Wei-Yi Wei was born in Tainan, Taiwan. He received the B.S degree in electrical engineering from the Electrical Engineering, National Chung-Hsing University, Taichung, Taiwan, in 2008, and the M.S. degree in communication engineering from the Graduate Institute of Communication Engineering, National Taiwan University, Taipei, Taiwan, in 2010.

    He joined the Realtek Semiconductor Corp., Hsinchu Science Park, Taiwan, in 2010, and is currently a digital IC designer with the IC Design Center, Switch, Communication Network Business Unit. His research interests include signal/image processing, image/video coding (JPEG, JPEG2000, JPEG-LS, MPEG-1/2/4, H.264/AVC), the digital IC design of Ethernet chipset (IEEE 802.3 MAC/PHY).

《Contact Information》

《Education》

  • Master of Science, Graduate Institute of Communication Engineering, National Taiwan University, 9/2008-6/2010.
  • Bachelor of Science, Department of Electrical Engineering, National Chung Hsing University, 9/2004-6/2008.

《Awards and Honors》

  • President's Awards (Top 5% in class) of NCHUEE, 7 times (Rank 1/45 in the last semester is exclusive).
  • Nominee, Soft IP Division, Silicon Iintellectual Property Contest, 2007.
  • Best Paper Award, The 22nd IPPR Conference on Computer Vision, Graphics and Image Processing, 2009.
  • Best Poster Award, International Conference paper on Asia Pacific Signal and Information Processing Association
  • 青年論文獎 第三名, 中國電機工程學會, 2010.
  • 98學年度最佳碩士學位論文獎, 國立台灣大學電信工程學研究所, 2010.

《Experience》

  • Teaching Assistant, Switching Circuit and Logic Design, Electrical Engineering Department, National Taiwan University, Taipei, Taiwan, Fall 2009.
  • Teaching Assistant, Signal and System, Electrical Engineering Department, National Taiwan University, Taipei, Taiwan, Spring 2009.
  • Digital IC Designer/Research and Development, Realtek, Hsinchu, Taiwan, 2010.

《Research Interests》

  • Image and Video Coding
  • Digital Signal and Image Processing
  • Digital System and Circuit Design

《Proficiencies》

  • Language: Verilog, SystemVerilog, Perl, VMM/RVM, HSPICE, C/C++, C#, Java, MATLAB.
  • Physical Design Tools: Cadence NCVerilog, Synopsys VCS, Synopsys Design Compiler, Synopsys PrimeTime, Synopsys PrimeTime-PX, Springsoft Debussy, Cadence LEC.

《Publication》

  • Master Thesis

  • [1] Wei-Yi Wei, "Image Coding by Adaptive Golomb Codes and the Information of Adjacent Blocks," National Taiwan University, May, 2012.

  • Journal Paper

  • [1] J. J. Ding, H. H. Chen, and Wei-Yi Wei, "Adaptive Golomb code for joint geometrically distributed data and its application in image coding," IEEE Trans. Circuits Syst. Video Technol, accepted, Aug. 2012.

  • Conference Paper

  • [1] J. J. Ding, Wei-Yi Wei, and G. C. Pan, "Modified Golomb Coding Algorithm for Asymmetric Two-Sided Geometric Distribution Data," EUSIPCO 2012, Bucharest, Romania, Aug. 2012.

  • [2] J. J. Ding, Wei-Yi Wei, and G. C. Pan, "Modified Golomb coding algorithm for asymmetric two-sided geometric distributed data," CVGIP, Chia-Yi, Taiwan, Aug. 2011.

  • [3] J. J. Ding, Wei-Yi Wei, and H. H. Chen, "Context-based adaptive zigzag scanning for image coding," International Conference on VCIP, Tainan, Nov. 2011.

  • [4] J. J. Ding, S. C. Pei, W. Y. Wei, H. H. Chen, and T. H. Lee, "Adaptive Golomb code for joint geometrically distributed data and its application in image coding," APSIPA Annual Summit and Conference, Biopolis, Singapore, Dec. 2010. (Best Poster Award)

  • [5] Wei-Yi Wei, Hsin-Hui Chen, and Jian-Jiun Ding, "Improved Advanced Image Coding Based on DC Intra Prediction Mode," CVGIP, Aug. 2010.

  • [6] Wei-Yi Wei, Hsin-Hui Chen, and Jian-Jiun Ding, "Context-Based Adaptive Zigzag Scanning For Image Coding," CVGIP, Aug. 2010.

  • [7] S. C. Pei, J. J. Ding, Wei-Yi Wei, and T. H. H. Lee, "Improved Golomb Code For Joint Geometric Distribution Data And Its Applications In Image Processing," CVGIP, Aug. 2009. (Best Paper Award)

  • [8] Yun-Ching Tang, Do-Chen Hu, Wei-Yi Wei, Wen-Chung Lin, and Hongchin Lin, "A Memory-efficient Architecture for Low Latency Viterbi Decoders," International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 2009.

  • Contest

 

Last Updated:2013/07/14


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